Various computer central processor instruction sets are used today. One type of them, the Advanced Reduced Instruction Set Computing (RISC) Machines (ARM) architecture, provides optional hardware (HW) extensions support or HW virtualization support. For instance, in ARM version 7 (ARMv7), as introduced in 2004, and in ARM version 8 (ARMv8) architectures, such HW virtualization support is present and supported.
Even though ARM adds HW features to support virtualization, there is still a need for hypervisor software in order to handle virtualization events. Hypervisor software, as compared to HW-based virtualization solution, provides flexibility in the form of easy extensibility of virtualization features, but downsizes its performance overhead due to lack of HW acceleration on software (SW) handled operations. One area that is affected by this performance overhead is the virtual timer interrupt delivery in ARM platforms.